Many electrical circuits require voltages to be boosted higher than the supply voltage of the circuit. One prior art method to provide a boosted voltage is a switched capacitor voltage doubler circuit. This method samples an input voltage, e.g., the supply voltage, on a capacitor during one phase and then connects the capacitor in series with the input voltage during a second phase to create a boosted output voltage at the top plate of the capacitor is equal to twice the input voltage. This same circuit is often used as a clock booster by connecting the capacitor in series with a clock voltage during the second phase. Because prior art clock boosters or voltage doublers are designed to boost the output voltage to double the supply voltage, they do not provide a boosted voltage that is between the supply voltage and double the supply voltage that may be useful in many designs.
This problem can be resolved with a variation of the voltage doubler by sampling the supply voltage, e.g., VDD, on the capacitor in the first phase and then connecting the capacitor in series with a boosting voltage in the second phase so that the top plate of the capacitor is boosted to the sum of the supply voltage, VDD, and the boosting voltage. Conversely, a boosting voltage can first be sampled on the capacitor in the first phase and then the capacitor is connected in series with the supply voltage, VDD, in the second phase so that the boosted output is the sum of the supply voltage, VDD, and the boosting voltage. However, such a design requires a second low impedance voltage source to provide the boosting voltage and this requires extra power.
Another approach is to add an attenuator capacitor to a conventional voltage doubler circuit. In this approach, the attenuator capacitor is connected to the top plate of the boost capacitor. During the first phase, the input voltage, e.g., VDD, is sampled on the boost capacitor. During the second phase, VDD is connected to the bottom plate of the boost capacitor. The voltage at the top plate of the boost capacitor is attenuated by the capacitive divider action of the boost capacitor and the attenuator capacitor. The result is that the boosted output voltage at the top plate of the boost capacitor is between VDD and two times VDD, as determined by the capacitor values of the boost capacitor and the attenuator capacitor. The advantage of this approach is that only a single low impedance input voltage, e.g., VDD, is needed. However, the circuit relies on selecting the attenuating capacitor for a specific desired boosted output voltage and therefore does not provide a programmable boosted output voltage.
It is often desirable to use a series-pass switch at the output of a typical clock booster or voltage doubler circuit so that the boosted voltage is allowed to pass to the output only during the boosted phase, e.g., in the second phase. Such a switch must be on during the boosted phase and off during the charging phase, e.g., the first phase. Prior art boosters typically employ a PMOS series-pass switch with the gate of the series-pass switch tied to a fixed voltage, typically VDD, and the source tied to the boosted voltage node. Thus, when the boosted voltage node rises sufficiently above the supply, the PMOS series-pass switch turns on and the boosted voltage passes to the output. When the boosting voltage node drops below VDD plus the threshold voltage, VT, the PMOS switch shuts off. However, conventional booster circuits are not designed to adjust or program the voltage at the gate of the series-pass switch to ensure the series-pass switch is off in one phase and on in another phase. Conventional clock booster circuits also cannot program the boosted voltage required to enable the series-pass switch over a range of programmable boost voltages.